1. Field of Invention
The present invention relates to a test method for integrated circuits and an interposer used therefor.
2. Description of Related Art
For test methods for integrated circuits (IC), the MP method (IEC 61967-6), the VDE method (IEC 61967-4), and the like, which are defined according to the IEC (International Electrotechnical Commission), for example, are known. The MP and VDE methods are methods of measuring IC power current for evaluation. In addition, Japanese Patent Laid-Open No. 2007-085741 discloses a technique that evaluates noise emitted from a casing, in which electric current that flows through screws that fix a substrate to the casing and electric current that leaks from the substrate to the casing are determined and individually measured.
Now, in recent ICs, the number of terminals of the IC package tends to increase with the increase in multifunctionality and high density. On the other hand, there is also a requirement that the size of the IC package be reduced. BGA (Ball Grid Array) packages are known as an IC package that allows terminals to be packaged in high density. However, even for BGA packages, there are limitations governing the amount of terminals that can be included in a high density layout, and the requirement is that unnecessary terminals be eliminated.
ICs generally include pluralities of power supply terminals and ground terminals. However, because the test method of the Related Art cannot measure electric currents flowing through the individual terminals of the BGA package, for example, extra power supply terminals or ground terminals are sometimes provided, based on simulation results of current that is consumed, or the like.
The foregoing MP and VDE methods are methods of measuring the current consumption of the overall IC, but are not methods used for measuring electric currents flowing through individual terminals. Furthermore, although the technique described in Japanese Patent Laid-Open No. 2007-085741 can measure electric currents flowing through individual screws, the technique cannot measure electric currents flowing through individual terminals of the BGA package. Moreover, the technique described in Japanese Patent Laid-Open No. 2007-085741 cannot identify terminals that may be removed from the IC.